{
  "slug": "nvme",
  "term": "NVMe",
  "aliases": [
    "NVM Express",
    "NVMe protocol"
  ],
  "definition": "A host controller interface and command set optimized for PCIe-attached non-volatile memory such as NAND SSDs.",
  "note": "NVM Express is a register-level and command-set interface originally designed for PCIe-attached non-volatile memory, later generalized across transports (PCIe, RDMA, TCP). Hosts submit commands into memory-based submission queues, ring doorbells, and reap completion queues—supporting deep parallelism without AHCI/SCSI translation layers built for spinning disks. Form factors (M.2, U.2, EDSFF, AIC) carry NVMe over PCIe; the protocol is not itself a drive shape. The NVMe specification family splits Base, I/O command sets (NVM, ZNS, KV, etc.), and transport bindings. Compared with SATA/AHCI, NVMe targets lower latency and far higher queue depth and bandwidth for flash and future NVM.",
  "status": "shipping",
  "advantages": [
    {
      "text": "Lower per-command overhead and deeper queues than legacy SATA/AHCI for flash.",
      "citationIds": [
        "c1"
      ]
    }
  ],
  "limitations": [],
  "related": [
    "pcie-storage",
    "ssd",
    "enterprise-ssd",
    "m2",
    "u2",
    "edsff",
    "zns"
  ],
  "supersedes": [],
  "supersededBy": [],
  "firstSeen": {
    "date": "2014",
    "citationIds": [
      "c1"
    ]
  },
  "lastSeen": null,
  "citations": [
    {
      "id": "c1",
      "title": "NVM Express specifications",
      "url": "https://nvmexpress.org/specifications/",
      "accessed": "2026-03-26"
    },
    {
      "id": "n2",
      "title": "NVM Express — Base Specification page (spec family overview)",
      "url": "https://nvmexpress.org/specification/nvm-express-base-specification/",
      "accessed": "2026-10-07"
    },
    {
      "id": "n3",
      "title": "NVM Express — NVMe overview PDF",
      "url": "https://nvmexpress.org/wp-content/uploads/NVMe_Overview.pdf",
      "accessed": "2026-10-07"
    }
  ]
}